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M14D5121632A-3BIG 参数 Datasheet PDF下载

M14D5121632A-3BIG图片预览
型号: M14D5121632A-3BIG
PDF下载: 下载PDF文件 查看货源
内容描述: 8M ×16位×4银行DDR II SDRAM [8M x 16 Bit x 4 Banks DDR II SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 59 页 / 982 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
DC Specifications
(IDD values are for the operation range of Voltage and Temperature)
Parameter
Symbol
Test Condition
One bank;
t
CK
= t
CK
(IDD), t
RC
= t
RC
(IDD), t
RAS
= t
RAS
(IDD)min;
CKE is High, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
One bank; I
OUT
= 0mA;
BL = 4, CL = CL(IDD), AL = 0;
t
CK
= t
CK
(IDD), t
RC
= t
RC
(IDD),
t
RAS
= t
RAS
(IDD)min, t
RCD
= t
RCD
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
All banks idle;
t
CK
= t
CK
(IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
All banks idle;
t
CK
= t
CK
(IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
All banks idle;
t
CK
= t
CK
(IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open;
t
CK
= t
CK
(IDD); CKE is LOW;
Other control and address bus inputs
are STABLE;
Data bus input are FLOATING
Fast PDN Exit
MRS(12) = 0
Slow PDN Exit
MRS(12) = 1
M14D5121632A
Operation Temperature Condition (T
C
) -40
°
C~95
°
C
Version
-3
Unit
Operating Current
(Active - Precharge)
IDD0
65
mA
Operating Current
(Active - Read -
Precharge)
IDD1
80
mA
Precharge
Power-Down
Standby Current
IDD2P
10
mA
Precharge Quiet
Standby Current
IDD2Q
15
mA
Idle Standby Current IDD2N
20
mA
Active Power-down
Standby Current
IDD3P
15
mA
12
Active Standby
Current
IDD3N
All banks open;
t
CK
= t
CK
(IDD), t
RAS
= t
RAS
(IDD)max, t
RP
= t
RP
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open, continuous burst Reads, I
OUT
= 0mA;
BL = 4, CL = CL (IDD), AL = 0;
t
CK
= t
CK
(IDD), t
RAS
= t
RAS
(IDD)max, t
RP
= t
RP
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is the same as IDD4W;
All banks open, continuous burst Writes;
BL = 4, CL = CL (IDD), AL = 0;
t
CK
= t
CK
(IDD), t
RAS
= t
RAS
(IDD)max, t
RP
= t
RP
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
35
mA
Operation Current
(Read)
IDD4R
145
mA
Operation Current
(Write)
IDD4W
140
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2009
Revision : 1.1
6/59