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M14D5121632A-3BIG2H 参数 Datasheet PDF下载

M14D5121632A-3BIG2H图片预览
型号: M14D5121632A-3BIG2H
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.45ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1001 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M14D5121632A (2H)  
Operation Temperature Condition (TC) -40°C~95°C  
AC Operating Test Conditions  
Parameter  
Value  
0.5 x VDDQ  
1.0  
Unit  
V
Note  
1
Input reference voltage ( VREF  
)
Input signal maximum peak swing ( VSWING(max.) )  
Input signal minimum slew rate  
Input level  
V
1
1.0  
V/ns  
V
2,3  
VIH / VIL  
VREF  
Input timing measurement reference level  
V
Output timing measurement reference level (VOTR  
)
0.5 x VDDQ  
V
4
Note:  
1. Input waveform timing is referenced to the input signal crossing through the VIH / VIL (AC) level applied to the device under  
test.  
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH (AC) (min.) for rising edges and the  
range from VREF to VIL (AC)(max.) for falling edges as shown in the below figure.  
3. AC timings are referenced with input waveforms switching from VIL (AC) to VIH (AC) on the positive transitions and VIH (AC) to  
VIL (AC) on the negative transitions.  
4. The VDDQ of the device under test is reference.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Aug. 2011  
Revision : 1.1 10/62