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M14D5121632A-2.5BIG2H 参数 Datasheet PDF下载

M14D5121632A-2.5BIG2H图片预览
型号: M14D5121632A-2.5BIG2H
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.4ns, CMOS, PBGA84, 8 X 12.50 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, BGA-84]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1001 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
DC Specifications
(IDD values are for the operation range of Voltage and Temperature)
Parameter
Symbol
Test Condition
M14D5121632A (2H)
Operation Temperature Condition (T
C
) -40
°
C~95
°
C
Version
-1.8
-2.5
-3
Unit
Operating Current
(Active - Precharge)
IDD0
Operating Current
(Active - Read -
Precharge)
IDD1
One bank;
t
CK
= t
CK
(IDD), t
RC
= t
RC
(IDD), t
RAS
= t
RAS
(IDD)min;
CKE is High, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
One bank; I
OUT
= 0mA;
BL = 4, CL = CL(IDD), AL = 0;
t
CK
= t
CK
(IDD), t
RC
= t
RC
(IDD),
t
RAS
= t
RAS
(IDD)min, t
RCD
= t
RCD
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
All banks idle;
t
CK
= t
CK
(IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
All banks idle;
t
CK
= t
CK
(IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
All banks idle;
t
CK
= t
CK
(IDD); CKE is HIGH, CS is HIGH;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open;
t
CK
= t
CK
(IDD); CKE is LOW;
Other control and address bus inputs
are STABLE;
Data bus input are FLOATING
Fast PDN Exit
MRS(12) = 0
Slow PDN Exit
MRS(12) = 1
100
90
80
mA
120
110
110
mA
Precharge
Power-Down
Standby Current
IDD2P
15
15
15
mA
Precharge Quiet
Standby Current
IDD2Q
60
55
50
mA
Idle Standby Current IDD2N
60
55
50
mA
75
65
60
mA
Active Power-down
Standby Current
IDD3P
25
25
25
Active Standby
Current
IDD3N
All banks open;
t
CK
= t
CK
(IDD), t
RAS
= t
RAS
(IDD)max, t
RP
= t
RP
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
All banks open, continuous burst Reads, I
OUT
= 0mA;
BL = 4, CL = CL (IDD), AL = 0;
t
CK
= t
CK
(IDD), t
RAS
= t
RAS
(IDD)max, t
RP
= t
RP
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is the same as IDD4W;
All banks open, continuous burst Writes;
BL = 4, CL = CL (IDD), AL = 0;
t
CK
= t
CK
(IDD), t
RAS
= t
RAS
(IDD)max, t
RP
= t
RP
(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
95
80
75
mA
Operation Current
(Read)
IDD4R
230
190
180
mA
Operation Current
(Write)
IDD4W
240
200
190
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.1
6/62