ESMT
M14D5121632A (2A)
AC Timing Parameter & Specifications
-1.5
Unit
Note
Parameter
Symbol
Min.
1500
1500
1500
Max.
3000
3000
3000
ps
ps
ps
CL=7
CL=8
CL=9
t
CK (avg)
13
10
Clock period
DQ output access time from
CLK/ CLK
tAC
-350
+350
ps
CLK high-level width
CLK low-level width
t
CH (avg)
CL (avg)
0.48
0.48
0.52
0.52
t
t
CK (avg)
CK (avg)
13
13
t
DQS output access time from
CLK/ CLK
tDQSCK
-300
+300
ps
10
Clock to first rising edge of DQS
delay
tDQSS
-0.25
200
200
0.35
125
200
0.6
+0.25
t
t
t
CK (avg)
ps
Data-in and DM setup time
(to DQS)
tDS
(base)
4
5
Data-in and DM hold time
(to DQS)
tDH
(base)
ps
DQ and DM input pulse width
(for each input)
tDIPW
CK (avg)
ps
Address and Control Input
setup time
t
IS (base)
4
5
Address and Control Input hold
time
t
IH (base)
tIPW
ps
Control and Address input pulse
width
CK (avg)
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.44
0.44
t
t
CK (avg)
CK (avg)
DQS falling edge to CLK rising
setup time
tDSS
tDSH
0.2
0.2
t
t
CK (avg)
CK (avg)
ps
DQS falling edge from CLK
rising hold time
Data strobe edge to output data
edge
tDQSQ
250
Data-out high-impedance
window from CLK/ CLK
tHZ
t
AC(max.)
ps
ps
ps
ps
10
10
tLZ
(DQS)
tLZ
Data-out low-impedance window
from CLK/ CLK
tAC(min.)
tAC(max.)
tAC(max.)
DQ low-impedance window from
CLK/ CLK
2 x tAC(min.)
10
(DQ)
Min
(tCL(abs),tCH(a
bs))
Half clock period
tHP
6,13
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2016
Revision : 1.0
11/64
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
