ESMT
M13S64164A
Operation Temperature Condition -40°C~85°C
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
tC L
tC K
0
1
2
3
4
5
6
7
8
9
10
C L K
C L K
tH P
N o t e 1
H I G H
C K E
t I S
t I H
C S
R A S
C A S
BAa
B A 0 , B A 1
BAb
A1 0 /AP
A D D R
(A 0~ An )
BAa
C b
W E
tR P S T
tD Q S S
tW P R E
tD Q S C K
tR P R E
tD Q S C K
t W P S T
tD Q S L
tDH
H i - Z
H i - Z
DQ S
tD Q S H
tW P R E S
tD Q S Q
tA C
tDS tDH tDS
tH Z
H i - Z
tL Z
H i - Z
Db3
D a 0
tQ H
D a 1
Db0
Db2
Db1
D Q
D M
D a 2
D a 3
C O M M A N D
READ
WRITE
Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2009
Revision : 1.0 32/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
