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M13S64164A-5BG 参数 Datasheet PDF下载

M13S64164A-5BG图片预览
型号: M13S64164A-5BG
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×16位×4银行双倍数据速率SDRAM [1M x 16 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 48 页 / 1552 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
DC Specifications
Parameter
Operation Current
(One Bank Active)
Operation Current
(One Bank Active)
Precharge Power-down
Standby Current
Idle Standby Current
Active Power-down Standby
Current
Active Standby Current
Operation Current (Read)
Operation Current (Write)
Auto Refresh Current
Self Refresh Current
Operation Current
(4 bank interleaving)
Symbol
Test Condition
t
RC
= t
RC
(min), t
CK
= t
CK
(min),
Active – Precharge
Burst Length = 2, t
RC
= t
RC
(min),
CL= 2.5, I
OUT
= 0mA,
Active-Read-Precharge
CKE
V
IL
(max), t
CK
= t
CK
(min),
All banks idle
CKE
V
IH
(min), CS
V
IH
(min),
t
CK
= t
CK
(min)
All banks ACT, CKE
V
IL
(max),
t
CK
= t
CK
(min)
One bank; Active-Precharge,
t
RC
= t
RAS
(max), t
CK
= t
CK
(min)
Burst Length = 2, CL= 2.5 ,
t
CK
= t
CK
(min), I
OUT
= 0mA
Burst Length = 2, CL= 2.5 ,
t
CK
= t
CK
(min)
t
RC
t
RFC
(min)
CKE
0.2V
Burst Length = 4, t
RC
= t
RC
(min),
I
OUT
= 0mA
Version
-5
110
M13S64164A
-6
100
Unit Note
IDD0
mA
IDD1
130
110
mA
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
10
70
20
90
180
180
140
5
235
10
70
15
80
160
160
120
5
215
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
Note: 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
Input Crossing Point Voltage, CLK and CLK inputs
Symbol
V
IH
(AC)
V
IL
(AC)
V
ID
(AC)
V
IX
(AC)
0.7
0.5*V
DDQ
-0.2
Min
V
REF
+ 0.31
V
REF
- 0.31
V
DDQ
+0.6
0.5*V
DDQ
+0.2
Max
Unit
V
V
V
V
1
2
Note
Note1. V
ID
is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(V
DD
= 2.3V~2.7V, V
DDQ
=2.3V~2.7V, T
A
= 25 °C , f = 1MHz)
Parameter
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS ,
WE
)
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
Symbol
C
IN1
C
IN2
C
OUT
C
IN3
Min
2.5
2.5
4.0
4.0
Max
3.5
3.5
5.5
5.5
Unit
pF
pF
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.4
5/48