ESMT
M13S5121632A (2R)
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CLK/ CLK ), and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the
range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively
switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level.
6. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).
7.
t
QH = tHP - tQHS, where:
t
HP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts
for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one transition
followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew
and output pattern effects, and p-channel to n-channel variation of the output drivers.
8. The only time that the clock frequency is allowed to change is during self-refresh mode.
9. If refresh time or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a
valid READ can be executed.
10. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be
guaranteed by device design or tester correlation.
11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are
reference to a specific voltage level that specifies when the device output is no longer driving (tHZ) or begins driving
(tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long
as the calculation is consistent.
12. tDQSQ consists of data pin skew and output pattern effects and p-channel to n-channel variation of the output drivers
for any given cycle.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this
CLK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device.
When no writes were previously in progress on the bus, DQS will be transitioning from High- Z to logic LOW. If a
previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending
on tDQSS
.
14. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
15. For command/address input slew rate ≥ 1.0 V/ns.
16. For CLK & CLK slew rate ≥ 1.0 V/ns (single-ended).
17. Slew Rate is measured between VOH(AC) and VOL(AC).
18. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
19. tRPST end point and tRPRE begin point are not reference to a specific voltage level but specify when the device output is
no longer driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are
not critical as long as the calculation is consistent.
20. In all circumstances, tXSNR can be satisfied using tXSNR = tRFC(min) + 1*tCK
.
21. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2013
Revision : 1.3 11/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
