ESMT
M13S5121632A (2R)
AC Timing Parameter & Specifications – continued
-4
-5
-6
Parameter
Symbol
Unit
Note
min
max
min
max
min
max
Active to Precharge command
tRAS
tRC
40
70K
40
70K
42
70K
ns
ns
Active to Active / Auto Refresh
command period
55
70
55
70
60
72
Auto Refresh to Active / Auto Refresh
command period
tRFC
ns
Active to Read, Write delay
Precharge command period
tRCD
tRP
15
15
15
15
18
18
ns
ns
Active to Read with Auto Precharge
command
(tRCD
,
(tRCD
,
(tRCD,
tRAP
tRRD
ns
ns
tRAS
)
tRAS
)
tRAS
)
Active bank A to Active bank B
command
8
10
12
Write recovery time
tWR
tWTR
tREFI
15
2
15
2
15
1
ns
tCK
us
Write data in to Read command delay
Average periodic refresh interval
7.8
7.8
7.8
9-21
13
max(0.2
5* tCK
max(0.2
5* tCK
Write preamble
tWPRE
,
,
0.25
tCK
1.5ns)
1.5ns)
Write postamble
tWPST
tRPRE
tRPST
tWPRES
tMRD
0.4
0.6
1.1
0.6
0.4
0.6
1.1
0.6
0.4
0.9
0.4
0
0.6
1.1
0.6
tCK
tCK
tCK
ns
14
19
Read preamble
0.9
0.4
0
0.9
0.4
0
Read postamble
Clock to DQS write preamble setup time
Mode Register Set command cycle time
Exit self refresh to Read command
Exit self refresh to non-Read command
2
2
2
tCK
tCK
ns
tXSRD
tXSNR
200
75
200
75
200
75
20
(tWR/tCK
)
(tWR/tCK
)
(tWR/tCK
)
Auto Precharge write
recovery+precharge time
tDAL
+
+
+
tCK
(tRP/tCK
)
(tRP/tCK
)
(tRP/tCK)
Notes:
1. All voltages referenced to VSS
.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is
not intended to be either a precise representation of the typical system environment nor a depiction of the actual load
presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a
coaxial transmission line terminated at the tester electronics).
Elite Semiconductor Memory Technology Inc.
Publication Date : Feb. 2013
Revision : 1.3 10/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
