ESMT
AC Timing Parameter & Specifications
(V
DD
= 2.375V~2.625V, V
DDQ
=2.375V~2.625V, T
A
=0
°
C
to 70
°
C
)(Note)
Parameter
CL3
Clock Period
CL4
Access time from CLK/ CLK
CLK high-level width
CLK low-level width
Data strobe edge to clock edge
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
DQ and DM input pulse width (for each input)
M13S32321A
Symbol
min
5.0
t
CK
-
t
AC
t
CH
t
CL
t
DQSCK
t
DQSS
t
DS
t
DH
t
DIPW
t
IS
t
IH
t
IPW
t
DQSH
t
DQSL
t
DSS
t
DSH
t
DQSQ
t
HZ
t
LZ
-0.7
0.45
0.45
-0.7
0.75
0.5
0.5
1.75
1.0
1.0
2.2
0.4
0.4
0.2
0.2
-
-0.7
-0.7
-5
max
10
-
+0.7
0.55
0.55
+0.7
1.25
-
-
-
-
-
-
0.6
0.6
-
-
0.4
+0.7
+0.7
min
6.0
-
-0.7
0.45
0.45
-0.7
0.75
0.5
0.5
1.75
1.0
1.0
2.2
0.4
0.4
0.2
0.2
-
-0.7
-0.7
-6
max
10
ns
-
+0.7
0.55
0.55
+0.7
1.25
-
-
-
-
-
-
0.6
0.6
-
-
0.4
+0.7
+0.7
ns
t
CK
t
CK
ns
t
CK
ns
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
ns
ns
ns
Input setup time (fast slew rate)
Input hold time (fast slew rate)
Control and Address input pulse width
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
Data strobe edge to output data edge
Data-out high-impedance window from
CLK/
CLK
Data-out low-impedance window from
CLK/ CLK
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
7/50