ESMT
M13S32321A
Absolute Maximum Rating
Parameter
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
VDDQ
Value
Unit
V
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
V
V
TSTG
°C
W
Power dissipation
PD
IOS
1.0
50
Short circuit current
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to VSS = 0V, TA = 0 to 70 °C )
Parameter
Symbol
VDD
Min
2.375
Max
Unit
V
Note
Supply voltage
2.625
I/O Supply voltage
I/O Reference voltage
VDDQ
2.375
2.625
V
VREF
0.49*VDDQ
VREF - 0.04
VREF + 0.15
-0.3
0.51*VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
V
1
2
I/O Termination voltage (system)
Input logic high voltage
VTT
V
VIH (DC)
VIL (DC)
VIN (DC)
V
Input logic low voltage
V
V
-0.3
VDDQ + 0.3
VDDQ + 0.6
Input Voltage Level, CLK and CLK inputs
VID (DC)
V
0.36
Input Differential Voltage, CLK and CLK inputs
Input leakage current
II
μ A
μ A
3
-2
-5
2
5
Output leakage current
IOZ
Output High Current (Normal strength driver)
(VOUT =VDDQ-0.373V, min VREF, min VTT)
IOH
IOL
IOH
IOL
-16.8
+16.8
-9
mA
mA
mA
mA
Output Low Current (Normal strength driver)
(VOUT = 0.373V)
Output High Current (Weak strength driver)
(VOUT =VDDQ-0.763V, min VREF, min VTT)
Output Low Current (Weak strength driver)
(VOUT = 0.763V)
+9
Notes 1. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
2.
VTT is not applied directly to the device. VTT is system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF
.
3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK .
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1 4/50