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M13S256328A 参数 Datasheet PDF下载

M13S256328A图片预览
型号: M13S256328A
PDF下载: 下载PDF文件 查看货源
内容描述: 2M ×32位×4银行双倍数据速率SDRAM [2M x 32 Bit x 4 Banks Double Data Rate SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 47 页 / 786 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
AC Timing Parameter & Specifications-continued
Parameter
Half Clock Period
DQ-DQS output hold time
Data hold skew factor
(for DQS & associated DQ
signals)
ACTIVE to PRECHARGE
command
Row Cycle Time
AUTO REFRESH Row Cycle
Time
ACTIVE to READ delay
ACTIVE to WRITE delay
PRECHARGE command
period
ACTIVE to READ with
AUTOPRECHARGE
command
ACTIVE bank A to ACTIVE
bank B command
Write recovery time
Write data in to READ
command delay
Col. Address to Col. Address
delay
Average periodic refresh
interval
Write preamble
Write postamble
DQS read preamble
DQS read postamble
Clock to DQS write preamble
setup time
Load Mode Register /
Extended Mode register
cycle time
Exit self refresh to READ
command
Exit self refresh to
non-READ command
Autoprecharge write
recovery+Precharge time
Symbol
t
HP
t
QH
t
QHS
-5
min
t
CL
min or t
CH
min
M13S256328A
max
-
Unit
ns
ns
ns
t
HP
-tQHS
-
-
0.5
t
RAS
t
RC
t
RFC
t
RCDRD
t
RCDWT
t
RP
40
55
70
20
10
15
120Kns
-
-
-
-
-
ns
ns
ns
ns
ns
ns
t
RAP
15
-
ns
t
RRD
t
WR
t
WTR
t
CCD
t
REFI
t
WPRE
t
WPST
t
RPRE
t
RPST
t
WPRES
10
15
2
1
-
0.25
0.4
0.9
0.4
0
-
-
-
-
7.8
-
0.6
1.1
0.6
-
ns
ns
t
CK
t
CK
us
t
CK
t
CK
t
CK
t
CK
ns
t
MRD
2
-
t
CK
t
XSRD
t
XSNR
200
75
(t
WR
/t
CK
)
+
(t
RP
/t
CK
)
-
-
t
CK
ns
t
DAL
-
t
CK
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2
7/47