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M13S2561616A-6TIG2S 参数 Datasheet PDF下载

M13S2561616A-6TIG2S图片预览
型号: M13S2561616A-6TIG2S
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 49 页 / 1245 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
AC Operation Conditions & Timing Specifications
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CLK and CLK inputs
Input Crossing Point Voltage, CLK and CLK inputs
Notes:
Symbol
V
IH
(AC)
V
IL
(AC)
V
ID
(AC)
V
IX
(AC)
M13S2561616A (2S)
Operation Temperature Condition -40°C~85°C
Min
V
REF
+ 0.31
Max
Unit
V
Note
V
REF
- 0.31
0.7
0.5*V
DDQ
-0.2
V
DDQ
+0.6
0.5*V
DDQ
+0.2
V
V
V
1
2
1. V
ID
is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of
the same.
AC Overshoot / Undershoot Specification
Parameter
Pin
Address, Control
Data, Strobe, Mask
Address, Control
Data, Strobe, Mask
Address, Control
Data, Strobe, Mask
Address, Control
Data, Strobe, Mask
Value
-5 / -6
1.5
1.2
1.5
1.2
4.5
2.4
4.5
2.4
Unit
V
V
V
V
V-ns
V-ns
V-ns
V-ns
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above V
DD
Maximum undershoot area below V
SS
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2015
Revision : 1.0
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