ESMT
DDR SDRAM
Features
Double-data-rate architecture, two data transfers per clock cycle
Bi-directional data strobe (DQS)
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2, 2.5, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for READs; center-aligned with data for WRITEs
Data mask (DM) for write masking only
V
DD
= 2.375V ~ 2.625V, V
DDQ
= 2.375V ~ 2.625V
V
DD
= 2.5V ~ 2.7V, V
DDQ
= 2.5V ~ 2.7V (for speed -3.6)
Auto & Self refresh
32ms refresh period (4K cycle)
2.5V I/O (SSTL_2 compatible)
M13S128324A (2M)
1M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Ordering Information
Product ID
M13S128324A -3.6BG2M
M13S128324A -4BG2M
M13S128324A -5BG2M
M13S128324A -6BG2M
Max Freq.
275MHz (DDR550)
250MHz (DDR500)
200MHz (DDR400)
166MHz (DDR333)
V
DD
2.6V
2.5V
2.5V
2.5V
144 ball FBGA
Pb-free
Package
Comments
Elite Semiconductor Memory Technology Inc.
Publication Date : Aug. 2011
Revision : 1.3
1/48
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
