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M12S128324A-7TG 参数 Datasheet PDF下载

M12S128324A-7TG图片预览
型号: M12S128324A-7TG
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×32位×4银行同步DRAM [1M x 32 Bit x 4 Banks Synchronous DRAM]
分类和应用: 动态存储器
文件页数/大小: 46 页 / 742 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT
CAPACITANCE
(V
DD
= 2.5V, T
A
= 25
°C , f = 1MHZ)
Parameter
Input capacitance (A0 ~ A11, BA0 ~ BA1)
Input capacitance
(CLK, CKE, CS , RAS , CAS ,
WE
& DQM)
Data input/output capacitance (DQ0 ~ DQ31)
Symbol
CIN1
CIN2
COUT
Min
2
2
2
M12S128324A
Max
4
4
5
Unit
pF
pF
pF
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted,T
A
= 0 to 70 °C
Test Condition
Burst Length = 1
I
CC1
I
CC2P
I
CC2PS
I
CC2N
I
CC2NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3P
I
CC3PS
I
CC3N
t
RC
t
RC(min)
I
OL
= 0 mA
CKE
V
IL
(max), tcc = 10ns
CKE & CLK
V
IL
(max), t
cc
=
CKE
V
IH
(min), CS
V
IH
(min), t
cc
= 10ns
Input signals are changed one time during 20ns
CKE
V
IH
(min), CLK
V
IL
(max), t
cc
=
input signals are stable
CKE
V
IL
(max), tcc = 10ns
CKE & CLK
V
IL
(max), t
cc
=
CKE
VIH(min), CS
V
IH
(min), tcc = 15ns
Input signals are changed one time during 2clks
All other pins
V
DD
-0.2V or
0.2V
I
CC3NS
CKE
V
IH
(min), CLK
V
IL
(max), tcc =
input signals are stable
I
OL
= 0 mA
Page Burst
2 Banks activated
t
CK
= t
CK(min)
t
RC
t
RC(min)
CKE
0.2V
10
mA
110
0.8
mA
0.6
25
mA
7
3
3
30
mA
mA
90
mA
1,2
Version
-6
-7
Unit
Note
Parameter
Symbol
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Note :
I
CC4
180
160
mA
1,2
I
CC5
I
CC6
180
2
160
mA
mA
1. Measured with outputs open. Addresses are changed only one time during t
CC(min)
.
2. Refresh period is 64ms. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posed to
any given SDRAM, and the maximum absolute internal between any AUTO REFRSH command and the next AUTO
REFRESH command is 8x15.6μm. Addresses are changed only one time during t
CC(min)
.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4
5/46