ESMT
M12S128168A
(b) CL = 3 , B L= 4
CLK
i ) C M D
W R
D0
R D
R D
R D
R D
R D
D Q M
D Q
D1
D2
D3
W R
i i ) C M D
D Q M
D Q
D0
D1
D2
D3
i i i ) C M D
W R
D Q M
D Q
D3
D2
D1
D0
D2
D1
W R
i v ) C M D
D Q M
D Q
H i - Z
D0
D1
D3
v ) C M D
W R
D Q M
D Q
H i - Z
D2
D3
Q0
D0
* N o t e 1
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
C LK
*
N o t e 3
P R E
W R
CMD
*
N
o t e 2
DQM
DQ
D
D1
D
3
0
D2
tRD L(m in)
M
a
s
k
e
d
b
y
D Q M
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of four banks operation.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2008
Revision: 1.1 20/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
