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M12L64164A-5TIG2M 参数 Datasheet PDF下载

M12L64164A-5TIG2M图片预览
型号: M12L64164A-5TIG2M
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 4MX16, 4.5ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-54]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 45 页 / 1259 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
M12L64164A (2M)  
Operation Temperature Condition -40°C~85°C  
Note:  
1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.  
2. Bank active @ read/write are controlled by BA0, BA1.  
BA0  
BA1  
Active & Read/Write  
Bank A  
0
0
1
1
0
1
0
1
Bank B  
Bank C  
Bank D  
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command  
A10/AP  
BA0  
0
BA1  
0
Operating  
Disable auto precharge, leave A bank active at end of burst.  
Disable auto precharge, leave B bank active at end of burst.  
Disable auto precharge, leave C bank active at end of burst.  
Disable auto precharge, leave D bank active at end of burst.  
Enable auto precharge , precharge bank A at end of burst.  
Enable auto precharge , precharge bank B at end of burst.  
Enable auto precharge , precharge bank C at end of burst.  
Enable auto precharge , precharge bank D at end of burst.  
0
1
0
1
0
1
1
0
0
0
1
1
1
0
1
1
4. A10/AP and BA0, BA1 control bank precharge when precharge is asserted.  
A10/AP  
BA0  
0
BA1  
0
Precharge  
Bank A  
0
0
0
0
1
0
1
Bank B  
1
0
Bank C  
1
1
Bank D  
X
X
All Banks  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jun. 2012  
Revision: 1.2 28/45  
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