ESMT
M12L2561616A (2S)
Operation Temperature Condition -40°C~85°C
6. Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
C L K
C M D
D Q
C L K
C M D
P R E C L = 2
R D
P R E
W R
D 0
* N o t e 2
D Q ( C L 2 )
C M D
Q0
Q1
Q3
Q2
P R E
Q1
D 1
D 2
D 3
t
R D L
C L = 3
* N o t e 1
* N o t e 2
D Q ( C L 3 )
Q 2
Q 0
Q3
.
7. Auto Precharge
1 )N or m al W ri t e (B L = 4)
2 )N o rm al R e ad (B L = 4)
C L K
CL K
CMD
C MD
D Q
W R
RD
D3
D2
D1
D3
D Q (CL 2 )
DQ (CL 3 )
D0
D1
D2
D 1
D 0
D2
tR D L ( mi n )
D3
D 0
* N o t e3
Au t o P rec h a rg e s ta r t s
* N o t e3
A ut o P re ch a rg e sta rt s
*Note: 1. tRDL: Last data in to row precharge delay.
2. Number of valid output data after row precharge: 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2015
Revision: 1.4 20/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
