ESMT
M12L2561616A (2K)
Read & Write Cycle at Same Bank @ Burst Length = 4
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
11
12
10
C L O C K
H I GH
C K E
* N o t e 1
t
R C
C S
t
R C D
R A S
* N o t e 2
C A S
A D D R
BA0
Cb
Ca
R b
R a
BA1
A10/AP
C L = 2
Ra
Rb
Q a0 Q a1
D b 0 D b 1 D b 2 Db 3
D b0 Db 1 Db 2 Db 3
Q a 2 Q a 3
* N o t e 3
D Q
t
R D L
C L = 3
Qa 0 Qa 1
Q a3
Q a2
* N o t e 3
t
R D L
W E
DQ M
Precharge
( A - Bank )
Read
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Row Active
( A - Bank )
Pr ec ha r ge
( A - Ba nk )
: D o n ' t C a r e
*Note:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2012
Revision: 1.4 30/45
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
