欢迎访问ic37.com |
会员登录 免费注册
发布采购

M12L16161A-6T 参数 Datasheet PDF下载

M12L16161A-6T图片预览
型号: M12L16161A-6T
PDF下载: 下载PDF文件 查看货源
内容描述: 512K X 16位X 2Banks同步DRAM [512K x 16Bit x 2Banks Synchronous DRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 27 页 / 568 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
 浏览型号M12L16161A-6T的Datasheet PDF文件第1页浏览型号M12L16161A-6T的Datasheet PDF文件第2页浏览型号M12L16161A-6T的Datasheet PDF文件第3页浏览型号M12L16161A-6T的Datasheet PDF文件第5页浏览型号M12L16161A-6T的Datasheet PDF文件第6页浏览型号M12L16161A-6T的Datasheet PDF文件第7页浏览型号M12L16161A-6T的Datasheet PDF文件第8页浏览型号M12L16161A-6T的Datasheet PDF文件第9页  
M12L16161A
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C
V
IH
(min)/V
IL
(max)=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non power-
down mode
Symbol
I
CC1
I
CC2
P
I
CC2
PS
I
CC2
N
Test Condition
CAS
Version
Latency -4.3 -5 -5.5 -6 -7
-8
Unit Note
1
Burst Length = 1
t
RC
t
RC
(min),
t
CC
t
CC
(min), I
OL
= 0mA
CKE
V
IL
(max),
t
CC
=15ns
CKE
V
IL
(max), CLK
V
IL
(max),
t
CC
=
CKE
V
IH
(min), CS
V
IH
(min),
t
CC
=15ns
Input signals are changed one time during 30ns
CKE
V
IH
(min), CLK
V
IL
(max),
t
CC
=
Input signals are stable
CKE
V
IL
(max),
t
CC
=15ns
CKE
V
IL
(max), CLK
V
IL
(max),
t
CC
=
CKE
V
IH
(min), CS
V
IH
(min),
t
CC
=15ns
Input signals are changed one time during 30ns
CKE
V
IH
(min), CLK
V
IL
(max),
t
CC
=
Input signals are stable
I
OL
= 0Ma, Page Burst
All Band Activated,
t
CCD
=
t
CCD
(min)
3
2
250 230 210 190 160 140 mA
2
2
30
2
10
10
40
10
mA
mA
mA
mA
mA
mA
I
CC2
NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down
mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
I
CC3
P
I
CC3
PS
I
CC3
N
I
CC3
NS
I
CC
4
270 250 230 210 180 160 mA
270 250 230 210 180 160
270 250 230 210 180 160 mA
1
mA
1
I
CC
5
I
CC
6
t
RC
t
RC
(min)
CKE
0.2V
2
Note:
1.Measured with outputs open. Addresses are changed only one time during
t
CC
(min).
2.Refresh period is 32ms. Addresses are changed only one time during
t
CC
(min).
Elite Semiconductor Memory Technology Inc.
P.4
Publication Date : Jan. 2000
Revision : 1.3u