ESMT
M12L128324A
Operation temperature condition -40°C~85°C
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
0
1
2
3
4
5
6
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8
9
10
11
12
13
14
15
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17
18
19
C L O C K
H I G H
C K E
C S
R A S
C A S
A D D R
CA a
CA b
RA a
BA1
BA0
* N o t e 1
* N o t e 1
A10/AP
CL= 2
RA a
* N o t e 2
1
1
QAb3 QAb4
QAb1 QAb2
QAb5
QAa0
QAa2 QAa3 QAa4
QAb0
QAa1
QAa0
D Q
2
2
CL= 3
QAa2 QAa3 QAa4
QAa1
QAb0
QAb3 QAb4
QAb5
QAb1 QAb2
W E
D Q M
Read
(A - Ban k )
Burst Stop
Read
(A - Ban k )
Precharge
( A- B an k )
Row A c t i ve
( A- B an k )
:D on ' t C ar e
*Note : 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the lable 1,2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1 42/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
