ESMT
M12L128324A
Operation temperature condition -40°C~85°C
If both BA1 is “High” and BA0 is “Low” at read ,write , row active and precharge ,bank C is selected.
If both BA1 and BA0 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , BA1 and BA0 is ignored and all banks are selected.
5.During burst read or write with auto precharge. new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A11
BA0~BA1
RFU
A10/AP
RFU
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
RFU
W.B.L
TM
CAS Latency
Burst Length
Test Mode
CAS Latency
Burst Type
Burst Length
A8
0
A7
Type
A6
0
A5
0
A4
0
Latency
Reserved
1
A3
Type
A2
0
A1
0
A0
0
BT = 0
BT = 1
0
1
0
1
Mode Register Set
Reserved
0
1
Sequential
Interleave
1
2
4
8
1
2
4
8
0
0
0
1
0
0
1
1
Reserved
0
1
0
2
0
1
0
1
Reserved
0
1
1
3
0
1
1
Write Burst Length
Length
1
0
0
Reserved
Reserved
Reserved
Reserved
1
0
0
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
A9
0
1
0
1
1
0
1
Burst
1
1
0
1
1
0
1
Single Bit
1
1
1
1
1
1
Full Page Length : 256
POWER UP SEQUENCE
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs.
2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “ Burst Read single Bit Write” function will be enabled.
3. The full column burst (256 bit) is available only at sequential mode of burst type.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2006
Revision: 1.1 11/49
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
