ESMT
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between V
IL
and V
IH
. During operation with CKE
high all inputs are assumed to be in valid state (low or high) for
the duration of setup and hold time around positive edge of the
clock for proper functionality and Icc specifications.
M12L128168A
Operation temperature condition -40
°
C ~85
°
C
POWER-UP
1.Apply power and start clock, Attempt to maintain CKE =
“H”, DQM = “H” and the other pins are NOP condition at
the inputs.
2.Maintain stable power, stable clock and NOP input
condition for minimum of 200us.
3.Issue precharge commands for both banks of the
devices.
4.Issue 2 or more auto-refresh commands.
5.Issue a mode register set command to initialize the
mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time same
as other inputs), the internal clock suspended from the next
clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with
clock, the SDRAM enters the power down mode from the next
clock cycle. The SDRAM remains in the power down mode
ignoring the other inputs as long as CKE remains low. The
power down exit is synchronous as the internal clock is
suspended. When CKE goes high at least “1CLK + t
SS
” before
the high going edge of the clock, then the SDRAM becomes
active from the same clock edge accepting all the input
commands.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the CAS
latency, burst type, burst length, test mode and various
vendor specific options to make SDRAM useful for variety
of different applications. The default value of the mode
register is not defined, therefore the mode register must
be written after power up to operate the SDRAM. The
mode register is written by asserting low on CS , RAS ,
CAS and
WE
(The SDRAM should be in active mode
with CKE already high prior to writing the mode register).
The state of address pins A0~A11 and A13~A12 in the
same cycle as CS , RAS , CAS and
WE
going low is
the data written in the mode register. Two clock cycles is
required to complete the write in the mode register. The
mode register contents can be changed using the same
command and clock cycle requirements during operation
as long as all banks are in the idle state. The mode
register is divided into various fields into depending on
functionality. The burst length field uses A0~A2, burst type
uses A3, CAS latency (read latency from column address)
use A4~A6, vendor specific options or test mode use
A7~A8, A10/AP~A11 and A13~A12. The write burst length
is programmed using A9. A7~A8, A10/AP~A11 and
A13~A12 must be set to low for normal SDRAM
operation. Refer to the table for specific codes for various
burst length, burst type and CAS latencies.
BANK ADDRESSES (A13~A12)
This SDRAM is organized as four independent banks of
2,097,152 words x 16 bits memory arrays. The A13~A12
inputs are latched at the time of assertion of RAS and CAS
to select the bank to be used for the operation. The banks
addressed A13~A12 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0~A11)
The 21 address bits are required to decode the 2,097,152
word locations are multiplexed into 12 address input pins
(A0~A11). The 12 row addresses are latched along with RAS
and A13~A12 during bank active command. The 9 bit column
addresses are latched along with CAS ,
WE
and A13~A12
during read or with command.
NOP and DEVICE DESELECT
When RAS , CAS and
WE
are high , The SDRAM
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which require
more than single clock cycle like bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is
entered by asserting
CS
high.
CS
high disables the
command decoder so that RAS , CAS ,
WE
and all the
address inputs are ignored.
BANK ACTIVATE
The bank activate command is used to select a random
row in an idle bank. By asserting low on RAS and CS
with desired row and bank address, a row access is
initiated. The read or write operation can occur after a
time delay of t
RCD(min)
from the time of bank activation. t
RCD
is the internal timing parameter of SDRAM, therefore it is
dependent on operating clock frequency. The minimum
number of clock cycles required between bank activate
and read or write command should be calculated by
Elite Semiconductor Memory Technology Inc.
Publication Date: Oct. 2007
Revision: 1.2
10/43
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
