ESMT
(Preliminary)
M12L128324A (2E)
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3, Burst Length = 1
tC H
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
tC L
tC C
H I G H
tR A S
tR C
tS H
* N o t e 1
C S
tR C D
tR P
tS S
tS H
tS S
R A S
C A S
tC C D
tS H
tS S
tS H
A D D R
R b
C c
R a
C a
C b
tS S
* N o t e 2 , 3
* N o t e 4
* N o t e 2 , 3
* N o t e 2
* N o t e 2
* N o t e 2 , 3
B S
BS
BS
BS
BS
BA0, BA1
A10/AP
D Q
BS
* N o t e 3
* N o t e 3
* N o t e 4
* N o t e 3
R b
R a
tS H
tS A C
Qc
Qa
D b
tS L Z
tS S
tO H
tS H
W E
tS S
tS S
tS H
D Q M
Ro w A c t i ve
Rea d
Read
Row A c t i ve
W r i t e
Precha rge
: D o n ' t C a r e
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1 27/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
