ESMT
(Preliminary)
M12L128324A (2E)
8. Burst Stop & Interrupted by Precharge
1 ) W r i t e B u r s t S t o p ( B L = 8 )
1 ) W r i t e i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
C L K
C M D
C M D
W R
D 0
P R E
W R
D 0
S T O P
t
R D L
* N o t e 1
D Q M
D Q
D Q M
D Q
D 2 M a s k
D 3
D 1
D 4
D 5
D 1
D 2
* N o t e 2
t
B D L
2 ) R e a d B u r s t S t o p ( B L = 4 )
2 ) R e a d i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
C L K
* N o t e 3
C M D
C M D
S T O P
Q 0
R D
P R E
Q 0
R D
* N o t e 3
D Q ( C L 2 )
D Q ( C L 3 )
Q1
Q0
D Q ( C L 2 )
D Q ( C L 3 )
Q 1
Q0
Q1
Q1
9. MRS
1 ) Mo d e R e g i s t e r S e t
CLK
* N o t e 4
C M D
AC T
PR E
M R S
tR P
2 C L K
*Note: 1. tRDL: 2 CLK; Last data in to Row Precharge.
2. tBDL: 1 CLK; Last data in to burst stop delay.
3. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely.
4. PRE: All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1 21/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
