ESMT
(Preliminary)
M12L128324A (2E)
6. Precharge
2 ) N o r m a l R e a d ( B L = 4 )
1 ) N o r m a l W r i t e ( B L = 4 )
CLK
CLK
D Q
C M D
CL= 2
Q3
PR E
Q2
PR E
R D
W R
D0
1 * N o t e 2
DQ ( C L 2 )
D1
Q0
D2
D3
Q1
Q0
tR D L
C M D
PR E
CL= 3
Q2
* N o t e 1
2 * N o t e 2
DQ ( C L 3 )
Q3
Q1
.
7. Auto Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
CLK
CLK
C M D
R D
C M D
D Q
W R
Q1
Q0
Q2
Q0
D0
Q3
Q2
D1
D2
D3
DQ ( C L 2 )
DQ ( C L 3 )
tR D L
Q1
Q3
* N o t e 3
Auto Pr ech ar ge st art s
* N o t e 3
Auto Pr ech arge st art s
*Note: 1. tRDL: Last data in to row precharge delay.
2. Number of valid output data after row precharge: 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2011
Revision: 0.1 20/44
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
