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M11B416256A-35J 参数 Datasheet PDF下载

M11B416256A-35J图片预览
型号: M11B416256A-35J
PDF下载: 下载PDF文件 查看货源
内容描述: 256千×16 EDO DRAM页模式 [256 K x 16 DRAM EDO PAGE MODE]
分类和应用: 动态存储器
文件页数/大小: 15 页 / 375 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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EliteMT  
(Continued)  
M11B416256A  
-25  
-28  
-30  
-35  
-40  
UNIT Notes  
PARAMETER  
SYMBOL  
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX  
Read Command Setup Time  
Read Command Hold Time Reference to  
CAS  
tRCS  
tRCH  
0
0
0
0
0
0
0
0
0
0
ns  
ns  
15,18  
9,15,19  
Read Command Hold Time Reference to  
RAS  
tRRH  
tCLZ  
0
3
0
3
0
3
0
3
0
3
ns  
ns  
9
20  
CAS to Output in Low-Z  
Output Buffer Turn-off Delay From CAS  
or RAS  
10,17,2  
0
tOFF1  
tOFF2  
3
15  
6
3
15  
7
3
15  
8
3
15  
8
3
15  
8
ns  
ns  
ns  
ns  
ns  
17,26  
Output Buffer Turn-off to OE  
11,15,1  
tWCS  
tWCH  
tWCR  
0
5
0
5
Write Command Setup Time  
0
5
0
5
0
5
8
Write Command Hold Time  
Write Command Hold Time (Reference  
to RAS )  
15,25  
15  
22  
24  
26  
30  
34  
Write Command Pulse Width  
tWP  
tRWL  
tCWL  
5
7
5
7
5
8
5
9
5
ns  
ns  
15  
15  
10  
Write Command to RAS Lead Time  
5
0
5
5
0
5
6
0
5
7
0
5
8
0
5
ns  
ns  
ns  
ns  
15,19  
12,20  
12,20  
Write Command to CAS Lead Time  
Data-in Setup Time  
tDS  
tDH  
Data-in Hold Time  
tDHR  
tRWD  
tAWD  
tCWD  
22  
24  
26  
30  
34  
Data-in Hold Time (Reference to RAS )  
RAS to WE Delay Time  
34  
21  
17  
38  
25  
19  
46  
31  
25  
51  
34  
26  
56  
36  
27  
ns  
ns  
ns  
ns  
ms  
11  
11  
Column Address to WE Delay Time  
11,18  
2,3  
CAS to WE Delay Time  
Transition Time (rise or fall)  
Refresh Period (512 cycles)  
tT  
tREF  
1.5 50 1.5 50  
8 8  
1.5 50 2.5 50 2.5 50  
8 8 8  
tRPC  
tCSR  
tCHR  
10  
5
10  
5
10  
10  
10  
10  
10  
10  
10  
10  
10  
ns  
ns  
ns  
RAS to CAS Precharge Time  
CAS Setup Time(CBR REFRESH)  
CAS Hold Time(CBR REFRESH)  
1,18  
1,19  
7
7
OE Hold Time From WE During  
Read-Mode-Write Cycle  
tOEH  
4
4
4
4
5
ns  
16  
tOES  
tOEHC  
tOEP  
4
2
2
4
2
2
4
2
2
4
2
2
5
2
2
ns  
ns  
ns  
OE Low to CAS High Setup Time  
OE High Hold Time From CAS High  
OE Precharge Time  
OE Setup Prior to RAS During Hidden  
Refresh Cycle  
tORD  
0
0
0
0
0
ns  
Last CAS Going Low to First CAS  
Returning High  
tCLCH  
4
5
5
5
6
ns  
21  
Data Output Hold After CAS Returning  
Low  
tCOH  
tWHZ  
3
3
3
3
3
3
3
3
3
3
ns  
ns  
7
7
7
7
7
Output Disable Delay From WE  
Elite Memory Technology Inc  
Publication Date : Feb. 2004  
Revision : 1.9 5/15  
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