EliteMT
M11B416256A
CAPACITANCE (Ta = 25 °C , VCC = 5V ± 10%)
PARAMETER
SYMBOL
CI1
TYP
MAX
5
UNIT
pF
Input Capacitance (address)
-
-
-
Input Capacitance (RAS , CASH, CASL , WE , OE )
CI2
7
pF
Output capacitance (I/O0~I/O15)
CI / O
10
pF
AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 °C , VCC =5V ± 10%, VSS = 0V) (note 14)
Test Conditions
Input timing reference levels : 0V, 3V
Output reference level : VOL= 0.8V, VOH=2.0V
Output Load : 2TTL gate + CL (50pF)
Assumed tT = 2ns
-25
-28
-30
-35
-40
PARAMETER
SYMBOL
UNIT Notes
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Read or Write Cycle Time
tRC
tRWC
tPC
43
65
10
32
48
70
11
35
55
85
12
37
65
95
14
42
75
105
16
ns
ns
Read Write Cycle Time
EDO-Page-Mode Read or Write Cycle Time
EDO-Page-Mode Read-Write Cycle Time
Access Time From RAS
ns
ns
ns
ns
22
22
tPCM
tRAC
tCAC
47
25
28
30
35
40
4
8
8
12
14
9
9
15
17
9
9
15
17
10
10
18
20
11
11
20
22
5,20
Access Time From CAS
tOAC
tAA
ns 13,20
ns
Access Time From OE
Access Time From Column Address
tACP
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
Access Time From CAS Precharge
RAS Pulse Width
tRAS
tRASC
tRSH
tRP
25 10K 28 10K
25 100K 28 100K
30
30
9
35
35
10
25
5
40
40
11
30
6
10K
10K
10K
RAS Pulse Width (EDO Page Mode)
RAS Hold Time
100K
100K
100K
8
15
4
9
17
5
25
20
5
RAS Precharge Time
CAS Pulse Width
tCAS
tCSH
tCP
10K
17
10K
19
24
19
10K
21
10K
25
10K
29
21
4
24
4
26
4
30
5
35
5
CAS Hold Time
CAS Precharge Time
RAS to CAS Delay Time
6,23
7,18
19
tRCD
tCRP
10
10
10
10
10
5
0
5
8
5
0
5
8
5
0
5
8
5
0
5
8
5
0
5
8
ns
ns
ns
ns
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
tASR
tRAH
tRAD
tASC
tCAH
13
13
15
17
20
8
RAS to Column Address Delay Time
Column Address Setup Time
0
5
0
5
0
5
0
5
0
5
ns
ns
18
18
Column Address Hold Time
Column Address Hold Time (Reference to
RAS )
tAR
22
12
24
15
26
15
30
18
34
20
ns
ns
tRAL
Column Address to RAS Lead Time
Elite Memory Technology Inc
Publication Date : Feb. 2004
Revision : 1.9 4/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
