ESMT
F49L800UA/F49L800BA
Table 12.
Controlled Program/Erase Operations(TA = 0C to 70C, VCC =2.7V~3.6V)
CE
-70
-90
Symbol
Description
Min.
Max.
Min.
Max.
Unit
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
70
90
ns
t
WC
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
sec
t
AS
AH
DS
DH
45
45
t
35
35
t
Data Hold Time
0
0
t
Output Enable Setup Time
0
0
t
OES
Read Recovery Time Before Write
0
0
t
GHEL
0
0
0
0
Setup Time
Hold Time
t
WE
WE
CE
WS
WH
t
Pulse Width
35
35
t
CP
Pulse Width High
30
30
CE
t
CPH
Programming Operation(note2)
Sector Erase Operation (note2)
9(typ.)
0.7(typ.)
9(typ.)
0.7(typ.)
t
t
WHWH1
WHWH2
Notes :
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2008
Revision: 1.6 23/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
