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F49L320BA 参数 Datasheet PDF下载

F49L320BA图片预览
型号: F49L320BA
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位( 4M ×8 / 2M ×16 ) 3V只有CMOS闪存 [32 Mbit (4M x 8/2M x 16) 3V Only CMOS Flash Memory]
分类和应用: 闪存
文件页数/大小: 55 页 / 544 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F49L320UA/F49L320BA  
Operation Temperature Condition -40°C~85°C  
status bits, just as in the standard program operation. See  
“Write Operation Status” f or more information.  
operation. Further writes of the Resume command are  
ignored. Another Erase Suspend command can be written  
after the device has resumed erasing.  
The system may also write the auto-select command  
sequence when the device is in the Erase Suspend mode.  
The device allows reading auto-select codes even at  
addresses within erasing sectors, since the codes are not  
stored in the memory array. When the device exits the  
auto-select mode, the device reverts to the Erase Suspend  
mode, and is ready for another valid operation.  
Auto-select Command  
The auto-select command sequence allows the host  
system to access the manufacturer and devices codes, and  
determine whether or not a sector is protected. Table 6  
shows the address and data requirements. This method is  
an alternative to that shown in Table 4, which is intended  
for PROM programmers and requires VID on address bit  
A9.  
After an erase-suspended program operation is complete,  
the system can once again read array data within  
non-suspended sectors. The system can determine the  
status of the program operation using the DQ7 or DQ6  
status bits, just as in the standard program operation. See  
“Write Operation Status” f or more information.  
The auto-select command sequence is initiated by writing  
two unlock cycles, followed by the auto-select command.  
The device then enters the auto-select mode, and the  
system may read at any address any number of times,  
without initiating another command sequence. The read  
cycles at address 04H, 08H, 0CH, and 00H retrieves the  
ESMT manufacturer ID. A read cycle at address 01H  
retrieves the device ID. A read cycle containing a sector  
address(SA) and the address 02H returns 01H if that  
sector is protected, or 00H if it is unprotected. Refer to  
Tables 1 and 2 for valid sector addresses.  
The system may also write the auto-select command  
sequence when the device is in the Erase Suspend mode.  
The device allows reading auto-select codes even at  
addresses within erasing sectors, since the codes are not  
stored in the memory array. When the device exits the  
auto-select mode, the device reverts to the Erase Suspend  
mode, and is ready for another valid operation.  
The system must write the Erase Resume command  
(address bits are “don’t care” as shown in Table 5) to exit  
the erase suspend mode and continue the sector erase  
The system must write the reset command to exit the  
auto-select mode and return to reading array data.  
7.3 Write Operation Status  
The device provides several bits to determine the  
RY/  
, DQ7, and DQ6 each offer a method for  
BY  
status of a write operation: RY/ , DQ7, DQ6, DQ5,  
determining whether a program or erase operation is  
complete or in progress.  
BY  
DQ3, DQ2, and. Table  
7
and the following  
subsections describe the functions of these bits.  
Table 7. Write Operation Status  
DQ7  
(Note1)  
DQ5  
(Note2)  
Status  
DQ6  
DQ3 DQ2  
RY/  
BY  
No  
N/A  
Embedded Program Algorithm  
Embedded Erase Algorithm  
Toggle  
0
0
0
0
DQ7  
0
Toggle  
Toggle  
No  
Toggle  
1
Toggle  
0
1
Reading Erase Suspended  
Sector  
In Progress  
1
N/A Toggle  
Reading Non-Erase  
Suspended Sector  
Erase Suspend Program  
Erase Suspended Mode  
Data  
DQ7  
Data  
Data Data Data  
1
0
0
Toggle  
Toggle  
0
1
N/A  
N/A  
N/A  
No  
Toggle  
Toggle  
N/A  
Embedded Program Algorithm  
DQ7  
Exceeded  
Time Limits  
Embedded Erase Algorithm  
Erase Suspend Program  
0
DQ7  
Toggle  
Toggle  
1
1
1
N/A  
0
0
Notes:  
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.  
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.  
See “DQ5: Exceeded Timing Limits” for more information.  
Elite Semiconductor Memory Technology Inc.  
Publication Date : Sep. 2008  
Revision: 1.1 17/55  
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