EFST
preliminary
F49L040A
DQ2: Toggle Bit II
DQ5: Exceeded Timing Limits
The “Toggle Bit II” on DQ2, when used with DQ6,
indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit II
DQ5 indicates whether the program or erase time has
exceeded the specified limits(internal pulse count).
Under these conditions DQ5 will produce a "1". This
time-out condition indicates that the program or erase
cycle was not successfully completed. Data Polling and
Toggle Bit are the only operating functions of the device
under this condition.
is valid after the rising edge of the final WE or CE ,
whichever happens first, in the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. This allows the system to continue to use
the other active sectors in the device.
erasure. (The system may use either
or
to
CE
OE
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-
suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or whether is in erase-suspended, but
cannot distinguish which sectors are selected for
erasure. Thus, both status bits are required for sector
and mode information. Refer to Table 6 to compare
outputs for DQ2 and DQ6.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination
Figure 18 shows the toggle bit algorithm in flowchart
form. See also the DQ6: Toggle Bit I subsection. Figure
20 shows the toggle bit timing diagram. Figure 21
shows the differences between DQ2 and DQ6 in
graphical form.
of sectors are bad.
If this time-out condition occurs during the
programming operation, it specifies that the sector
containing that byte is bad and this sector may not be
reused, however other sectors are still functional and
can be reused.
Reading Toggle Bits DQ6/ DQ2
Refer to Figure 18 for the following discussion.
Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on DQ7–DQ0 on the following read
cycle.
The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.
DQ3:Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If
additional sectors are selected for erasure, the entire
timeout also applies after each additional sector erase
command.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
should note whether the value of DQ5 is high (see the
section on DQ5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as DQ5
went high. If the toggle bit is no longer toggling, the
device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading array
data.
When the time-out is complete, DQ3 switches from “0”
to “1.” If the time between additional sector erase
commands from the system can be assumed to be less
than 50 µs, the system need not monitor DQ3.
When the sector erase command sequence is written,
the system should read the status on DQ7 (Data
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (except Erase Suspend)
are ignored until the erase operation is complete.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described earlier.
Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 6 shows the outputs for DQ3.
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.4
13/41
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
