EFST
preliminary
F49L040A
DQ7: Data Polling
DQ6:Toggle BIT I
The DQ7 indicates to the host system whether an
Embedded Algorithm is in progress or completed, or
whether the device is in Erase Suspend mode. The
Data Polling is valid after the rising edge of the final
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
pulse in the program or erase command sequence.
valid after the rising edge of the final
pulse in the
WE
WE
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum
programmed
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
to DQ7. This DQ7 status also applies to programming
during Erase Suspend. When the Embedded Program
algorithm is complete, the device outputs the true data
on DQ7. The system must provide the program address
to read valid status information on DQ7. If a program
address falls within a protected sector, Data Polling on
DQ7 is active for approximately 1 µs, then the device
returns to reading array data.
cause DQ6 to toggle. The system may use either
OE
or
to control the read cycles. When the operation is
CE
complete, DQ6 stops toggling.
When an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
During the Embedded Erase algorithm, Data Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status
information on DQ7.
The system can use DQ6 and DQ2 together to
determine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(i.e. the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sectors
are erasing or erase-suspended. Alternatively, the
system can use DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data Polling
on DQ7 is active for approximately 100 µs, then the
device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the
selected sectors that are protected.
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7~
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program
algorithm is complete. Table 6 shows the outputs for
Toggle Bit I on DQ6. Figure 18 shows the toggle bit
algorithm. Figure 20 shows the toggle bit timing
diagrams. Figure 21 shows the differences between
DQ2 and DQ6 in graphical form. Refer to the
subsection on DQ2: Toggle Bit II.
Output Enable (
) is asserted low. Refer to Figure 19,
OE
Data Polling Timings (During Embedded Algorithms),
Figure 17 shows the Data Polling algorithm.
Elite Flash Storage Technology Inc.
Publication Date : Aug. 2003
Revision: 0.4
12/41
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
