EFST
F49L004UA / F49L004BA
10.3 Hardware Reset Operation
Table 13. AC CHARACTERISTICS (for 40-pin TSOP package type)
Symbol
Description
All Speed Options
Unit
Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
RESET
T
READY1
READY2
Max
Max
Min
20
us
Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
RESET
T
500
500
ns
ns
Pulse Width (During Embedded
RESET
Algorithms)
T
RP
High Time Before Read(See Note)
RESET
Min
Min
50
0
ns
ns
T
T
RH
RY/
BY
Recovery Time(to
,
go low)
CE OE
RB
Notes :
Not 100% tested
Figure 23.
Timing Waveform (for 40-pin TSOP package type)
RESET
RY/B Y
CE, O E
RE S E T
tR H
tR P
tR e a d y 2
Reset T i mi ng NO T dur i ng Au tom at i c Al gor i th m s
tR e a d y 1
RY/B Y
tR B
CE, O E
RE S E T
tR P
Reset T im in g dur i ng A ut om ati c A lgor i th m s
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2003
Revision: 1.0 40/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
