EFST
F49L004UA / F49L004BA
Figure 21. Data Polling Timings (During Embedded Algorithms)
tR C
VA
Addr es s
VA
tA C C
tC E
C E
tC H
t O E
OE
tO E H
tD F
W E
tO H
H i gh - Z
H i gh - Z
C o m p l e m e n t
V a i l d D a t a
C o m p l e m e n t
T r u e
T r u e
DQ7
S t a t u s D a t a
Va i l d D a t a
S t a t u s D a t a
DQ 0~ DQ 6
tB U S Y
RY/B Y
Notes :
VA = Valid Address. Figure shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2003
Revision: 1.0 38/46
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
