EFST
4. PIN CONFIGURATIONS
4.1
32-pin PDIP
F49B002UA
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3 2 - P in
DIP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
D D
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
4.2
32-pin PLCC
V
CC
A17
A15
3
A16
A12
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ 0
WE
NC
2
1 32 31 30
5
6
7
8
9
10
11
12
13
14 15 16 1 7 18 19 2 0
DQ1
DQ2
GND
DQ3
DQ4
DQ5
DQ6
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
4.3 Pin Description
Symbol
A0~A17
DQ0~DQ7
CE
OE
WE
Pin Name
Address Input
Data Input/Output
Chip Enable
Output Enable
Write Enable
No connection
Power Supply
Ground
Functions
To provide memory addresses.
To output data when Read and receive data when Write.
The outputs are in tri-state when OE or CE is high.
To activate the device when CE is low.
To gate the data output buffers.
To control the Write operations.
Unconnected pin
To provide power
NC
V
CC
GND
Elite Flash Storage Technology Inc.
Publication Date : Sep. 2006
Revision: 1.4
2/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
