EFST
F49B002UA
7.4 More Device Operations
Hardware Data Protection
Logical Inhibit
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
Write cycles are inhibited by holding any one of
=
OE
= VIH. To initiate a write cycle,
VIL,
CE
= VIH or
WE
WE
must be a logical zero while
CE
and
is a
OE
logical one.
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Power Supply Decoupling
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between
Low VCC Write Inhibit
its VCC and GND.
When VCC is less than VLKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
Power-Up Sequence
device resets. Subsequent writes are ignored until VCC
The device powers up in the Read Mode. In addition,
the memory contents may only be altered after
successful completion of the predefined command
sequences.
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO
.
Power-Up Write Inhibit
Write Pulse "Glitch" Protection
If
=
= VIL and
= VIH during power up, the
OE
Noise pulses of less than 15 ns (typical) on
do not initiate a write cycle.
or
WE
WE
device does not accept commands on the rising edge of
. The internal state machine is automatically reset
CE
CE
WE
to reading array data on power-up.
Elite Flash Storage Technology Inc.
Publication Date : Jun. 2003
Revision: 1.2 10/33
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
