欢迎访问ic37.com |
会员登录 免费注册
发布采购

F25S04PA-50DG 参数 Datasheet PDF下载

F25S04PA-50DG图片预览
型号: F25S04PA-50DG
PDF下载: 下载PDF文件 查看货源
内容描述: 2.5V只有4兆位串行闪存,带有双输出 [2.5V Only 4 Mbit Serial Flash Memory with Dual Output]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 34 页 / 382 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
 浏览型号F25S04PA-50DG的Datasheet PDF文件第20页浏览型号F25S04PA-50DG的Datasheet PDF文件第21页浏览型号F25S04PA-50DG的Datasheet PDF文件第22页浏览型号F25S04PA-50DG的Datasheet PDF文件第23页浏览型号F25S04PA-50DG的Datasheet PDF文件第25页浏览型号F25S04PA-50DG的Datasheet PDF文件第26页浏览型号F25S04PA-50DG的Datasheet PDF文件第27页浏览型号F25S04PA-50DG的Datasheet PDF文件第28页  
ESMT  
(Preliminary)  
F25S04PA  
Table 12: AC OPERATING CHARACTERISTICS - Continued  
Normal 33MHz Fast 50 MHz  
Fast 86 MHz Fast 100 MHz  
Symbol  
Parameter  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
THLH  
THHH  
ns  
ns  
ns  
ns  
5
5
5
5
HOLD Low Hold Time  
5
5
5
5
HOLD High Hold Time  
3
THZ  
6
6
6
6
6
6
6
6
HOLD Low to High-Z Output  
3
TLZ  
HOLD High to Low-Z Output  
Output Hold from SCK Change  
Output Valid from SCK  
TOH  
TV  
TWHSL  
0
0
0
0
ns  
ns  
ns  
12  
20  
8
8
8
4
20  
20  
20  
Write Protect Setup Time before CE Low  
4
TSHWL  
ns  
100  
15  
3
100  
15  
3
100  
15  
3
100  
15  
3
Write Protect Hold Time after CE High  
Write Status Register Time  
TW  
TDP  
(typ.) 3  
(typ.) 3  
(typ.) 3  
(typ.) 3  
ms  
us  
3
CE High to Deep Power Down Mode  
CE High to Standby Mode ( for DP)  
CE High to Standby Mode (for RES)  
3
TRES1  
us  
us  
3
3
3
3
3
TRES2  
1.8  
1.8  
1.8  
1.8  
Note:  
1. Relative to SCK.  
2. TSCKH + TSCKL must be less than or equal to 1/ FCLK  
.
3. Value guaranteed by characterization, not 100% tested in production.  
4. Only applicable as a constraint for a Write status Register instruction when Block- Protection-Look (BPL) bit is set at 1.  
ERASE AND PROGRAMMING PERFORMANCE  
Limit  
Parameter  
Symbol  
Unit  
Typ2  
Max3  
Sector Erase Time  
TSE  
TBE  
TCE  
TBP  
TPP  
40  
100  
2
ms  
s
Block Erase Time  
0.4  
Chip Erase Time  
3
7
s
Byte Programming Time  
Page Programming Time  
Chip Programming Time  
Erase/Program Cycles1  
Data Retention  
7
0.8  
10  
3
us  
ms  
s
3
5
100,000  
20  
-
Cycles  
Years  
-
Notes:  
1. Not 100% Tested, Excludes external system level over head.  
2. Typical values measured at 25°C, 2.5V.  
3. Maximum values measured at 85°C, 2.3V.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May 2009  
Revision: 0.2 24/34  
 复制成功!