ESMT
(Preliminary)
F25S04PA
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write-Enable-
Latch bit in the Software Status Register to 1 allowing Write
operations to occur.
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
The WREN instruction must be executed prior to any Write
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
06
MSB
HIGH IMPENANCE
SO
Figure 12: Write Enable (WREN) Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write-Enable-
Latch bit to 0 disabling any new Write operations from occurring.
CE must be driven high before the WRDI instruction is
executed.
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
04
MSB
HIGH IMPENANCE
CE
SO
Figure 13: Write Disable (WRDI) Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2009
Revision: 0.2 16/34
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
