ESMT
(Preliminary)
F25S04PA
Fast Read Dual Output (50 MHz ~ 100 MHz)
The Fast Read Dual Output (3BH) instruction is similar to the
standard Fast Read (0BH) instruction except the data is output
on SI and SO pins. This allows data to be transferred from the
device at twice the rate of standard SPI devices. This instruction
is for quickly downloading code from Flash to RAM upon
power-up or for applications that cache code- segments to RAM
for execution.
The Fast Read Dual Output instruction is initiated by executing
an 8-bit command, 3BH, followed by address bits [A23 -A0] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 4 for the Fast Read
Dual Output sequence.
Figure 4: Fast Read Dual Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: May 2009
Revision: 0.2
12/34
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
