ESMT
(Preliminary)
F25L32QA
CE
MODE3
0
1
2
3
4
5
6
7
TRES1
SCK MODE0
AB
SI
MSB
HIGH IMPEDANCE
SO
Standby Current
Deep Power Down Current
(ISB2)
Figure 26: Release from Deep Power Down (RDP) Instruction
CE
30 31 32 33 34 35 36 37 38
0
1
2
3
4
5
6
7
8
9
MODE3
TRES2
SCK MODE0
SS
3 Dummy Bytes
SS
AB
SI
MSB
HIGH IMPEDANCE
SS
Electronic-Signature Data Out
SO
MSB
Standby
Current
Deep Power Down Current
(ISB2)
Figure 27: Read Electronic -Signature (RES) Sequence
Table 6: Electronic Signature Data
Command
Mode
Electronic Signature Data
Normal
15H
In secured OTP mode &
35H
75H
RES
non lock down (OTP_lock =0)
In secured OTP mode &
lock down (OTP_lock =1)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 0.2 30/42
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
