ESMT
(Preliminary)
F25L32QA
Quad Page Program
The Quad Page Program instruction allows many bytes to be
programmed in the memory by using four I/O pins (SIO0, SIO1,
SIO2 and SIO3). The instruction can improve programmer
performance and the effectiveness of application that have slow
clock speed <20MHz. For system with faster clock, this
instruction can’t provide more actual favors, because the required
internal page program time is far more than the time data flows in.
Therefore, we suggest that user can execute this command while
the clock speed <20MHz.
Prior to Quad Page Program operation, the Write Enable (WREN)
instruction must be executed and Quad Enable (QE) bit of Status
Register-2 must be set “1”. The other function descriptions are as
same as standard Page Program. See Figure 11 for the Quad
Page Program sequence.
CE
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32 3334 35 36 37 3839
MODE3
MODE0
SCK
SS
32
ADD.
MSB
ADD.
ADD.
4
5
0
1
0
1
4
5
0
1
0
1
4
0
SIO0
SIO1
SIO2
SIO3
4
5
4
5
SS
MSB
SS
SS
SS
5
6
7
1
2
3
DIN 0 DIN 1 DIN2 DIN3
DIN255
Figure 11: Quad Page Program Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 0.2 21/42
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
