ESMT
(Preliminary)
F25L32QA
Fast Read Quad Output (50 MHz ~ 100 MHz)
The Fast Read Quad Output (6B) instruction is similar to the Fast
Read Dual Output (3BH) instruction except the data is output on
bidirectional I/O pins (SIO0, SIO1, SIO2 and SIO3). A Quad
Enable (QE) bit of Status Register-2 must be set “1” to enable
Quad function. This allows data to be transferred from the device
at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction is initiated by executing
an 8-bit command, 6BH, followed by address bits [A23 -A0] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 7 for the Fast Read
Quad Output sequence.
CE
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40 4142 43 44 45 46
4748
MODE3
MODE0
SCK
IO0 switches from Input to Ouput
Dummy
6B
ADD.
MSB
ADD.
ADD.
4
5
0
1
0
4
0
0
4
0
SIO0
SIO1
SIO2
SIO3
4
5
4
MSB
HIGH IMPENANCE
HIGH IMPENANCE
HIGH IMPENANCE
1
5
1
1
5
6
7
1
2
3
5
N
N+1 N+2 N+3 N+4
DOU T DOUT DOUT DOU T DOUT
Note: The input data during the dummy clocks is “don’t care”.
However , the IO pins should be high-impefance piror to the falling edge of the first data clock.
Figure 7: Fast Read Quad Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 0.2 18/42
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
