ESMT
F25L32PA
Table 3: F25L32PA Block Protection Table
TOP
Status Register Bit
Protected Memory Area
Protection Level
BP2
BP1
0
BP0
Block Range
None
Address Range
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
None
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
0
Block 63
3F0000H –3FFFFFH
3E0000H –3FFFFFH
3C0000H –3FFFFFH
380000H –3FFFFFH
300000H –3FFFFFH
200000H –3FFFFFH
000000H –3FFFFFH
1
Block 62~63
Block 60~63
Block 56~63
Block 48~63
Block 32~63
Block 0~63
1
0
0
1
1
Block Protection (BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
WP pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
BP2, BP1, BP0 bits as long as WP is high or the Block-
Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to1.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0
10/36
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
