ESMT
F25L32QA (2S)
64K Byte Block Erase
The 64K-byte Block Erase instruction clears all bits in the
selected block to FFH. A Block Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write Enable (WREN) instruction must be
-A0]. Address bits [AMS -A16] (AMS = Most Significant address) are
used to determine the block address (BAX), remaining address
bits can be VIL or VIH. CE must be driven high before the
instruction is executed. The user may poll the BUSY bit in the
Software Status Register or wait TBE for the completion of the
internal self-timed Block Erase cycle. See Figure 13 for 64K Byte
Block Erase sequence.
executed. CE must remain active low for the duration of the any
command sequence. The Block Erase instruction is initiated by
executing an 8-bit command, D8H, followed by address bits [A23
CE
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE3
MODE0
SCK
ADD.
ADD.
ADD.
D8
SI
MSB
MSB
HIGH IMPENANCE
SO
Figure 13: 64K-byte Block Erase Sequence
32K Byte Block Erase
The 32K-byte Block Erase instruction clears all bits in the
selected block to FFH. A Block Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write Enable (WREN) instruction must be
-A0]. Address bits [AMS -A15] (AMS = Most Significant address) are
used to determine the block address (BAX), remaining address
bits can be VIL or VIH. CE must be driven high before the
instruction is executed. The user may poll the BUSY bit in the
Software Status Register or wait TBE for the completion of the
internal self-timed Block Erase cycle. See Figure 14 for 32K Byte
Block Erase sequence.
executed. CE must remain active low for the duration of the any
command sequence. The Block Erase instruction is initiated by
executing an 8-bit command, 52H, followed by address bits [A23
CE
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE3
MODE0
SCK
ADD.
ADD.
ADD.
52
SI
MSB
MSB
HIGH IMPENANCE
SO
Figure 14: 64K-byte Block Erase Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2013
Revision: 1.7 29/51
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
