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F25L08PA-50PAG 参数 Datasheet PDF下载

F25L08PA-50PAG图片预览
型号: F25L08PA-50PAG
PDF下载: 下载PDF文件 查看货源
内容描述: 3V只有8兆位串行闪存,配有双 [3V Only 8 Mbit Serial Flash Memory with Dual]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 32 页 / 489 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F25L08PA  
„ ELECTRICAL SPECIFICATIONS  
Absolute Maximum Stress Ratings  
(Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device.  
This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the  
operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device  
reliability.)  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C  
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V  
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V  
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W  
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C  
Output Short Circuit Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. )  
AC CONDITIONS OF TEST  
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns  
Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for 75MHz  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for 50MHz  
See Figures 28 and 29  
OPERATING RANGE  
Parameter  
Symbol  
VDD (for FCLK <= 50MHz)  
VDD (for FCLK = 100MHz)  
TA  
Value  
2.7 ~ 3.6  
3.0 ~3.6  
0 ~ 70  
Unit  
V
Operating Supply Voltage  
Ambient Operating Temperature  
Table 9: DC OPERATING CHARACTERISTICS  
Limits  
Max  
15  
Symbol  
IDDR1  
Parameter  
Test Condition  
Min  
Unit  
Read Current  
Standard  
Dual  
mA  
CE =0.1 VDD/0.9 VDD, SO=open  
CE =0.1 VDD/0.9 VDD, SO=open  
@33 MHz  
18  
20  
23  
Read Current  
@ 50MHz  
Standard  
Dual  
IDDR2  
mA  
Read Current  
@ 100MHz  
Program and Erase Current  
Standard  
Dual  
25  
28  
IDDR3  
IDDW  
mA  
mA  
CE =0.1 VDD/0.9 VDD, SO=open  
CE =VDD  
35  
ISB  
ILI  
ILO  
VIL  
VIH  
VOL  
VOH  
Standby Current  
30  
1
1
µA  
µA  
µA  
V
V
V
CE =VDD, VIN =VDD or VSS  
VIN=GND to VDD, VDD=VDD Max  
VOUT=GND to VDD, VDD=VDD Max  
VDD=VDD Min  
VDD=VDD Max  
IOL=100 µA, VDD=VDD Min  
IOH=-100 µA, VDD=VDD Min  
Input Leakage Current  
Output Leakage Current  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
0.8  
0.7 x VDD  
VDD-0.2  
0.2  
V
Table 10: LATCH UP CHARACTERISTIC  
Symbol  
Parameter  
Minimum  
Unit  
Test Method  
1
ILTH  
Latch Up  
100 + IDD  
mA  
JEDEC Standard 78  
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: Jul. 2009  
Revision: 1.7 22/32  
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