ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Figure 26: HOLD Timing Diagram
VCC
VCC (max)
Program, Erase and Write command is ignored
CE must track VCC
VCC (min)
Read command
is allowed
T
VSL
Device is fully
accessible
Reset
State
VWI
T
PUW
Time
Figure 27: Power-Up Timing Diagram
Table 14: Power-Up Timing and VWI Threshold
Unit
Parameter
Symbol
Min.
Max.
TVSL
TPUW
VWI
200
us
ms
V
VCC(min) to CE low
Time Delay before Write instruction
10
2
Write Inhibit Threshold Voltage
1
Note: These parameters are characterized only.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 26/32