ESMT
Note:
1.
2.
3.
4.
5.
6.
7.
F25L08PA
Operation: S
IN
= Serial In, S
OUT
= Serial Out, Bus Cycle 1 = Op Code
X = Dummy Input Cycles (V
IL
or V
IH
); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
One bus cycle is eight clock periods.
Sector Earse addresses: use A
MS
-A
12
, remaining addresses can be V
IL
or V
IH
Block Earse addresses: use A
MS
-A
16
, remaining addresses can be V
IL
or V
IH
To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.
The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.
8.
9.
The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 14H as
memory capacity.
10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR
can reset WREN.
11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.
12. Dual commands use bidirectional IO pins. D
OUT
and cont. are serial data out; others are serial data in.
13. Dual output data:
IO
0
= (D
6
, D
4
, D
2
, D
0
), (D
6
, D
4
, D
2
, D
0
)
IO
1
= (D
7
, D
5
, D
3
, D
1
), (D
7
, D
5
, D
3
, D
1
)
D
OUT0
D
OUT1
Elite Semiconductor Memory Technology Inc.
Publication Date:
Jul. 2009
Revision: 1.7
9/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
