ESMT
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L08PA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Auto Address Increment (AAI)
Programming, Write Status Register, Sector Erase, Block Erase,
or Chip Erase instructions, the Write Enable (WREN) instruction
must be executed first. The complete list of the instructions is
provided in Table 5. All instructions are synchronized off a high to
low transition of CE . Inputs will be accepted on the rising edge
of SCK starting with the most significant bit. CE must be driven
F25L08PA
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read ID, Read Status Register, Read Electronic Signature
instructions). Any low to high transition on CE , before receiving
the last bit of an instruction bus cycle, will terminate the
instruction in progress and return the device to the standby
mode.
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Operation
Read
Fast Read
Fast Read Dual
12,13
Output
Sector Erase
4
(4K Byte)
Block Erase
4,
(64K Byte)
Chip Erase
Page Program (PP)
Auto Address Increment
word programming
5
(AAI)
Read Status Register
6
(RDSR)
Enable Write Status
7
Register (EWSR)
50
MHz
Write Status Register
7
(WRSR)
Write Enable (WREN)
10
Write Disable (WRDI)/
Exit secured OTP mode
Enter secured OTP mode
(ENSO)
100
MHz
Read Electronic
8
Signature (RES)
RES
in secured OTP
mode & not lock down
RES
in secured OTP
mode & lock down
Jedec Read ID
9
(JEDEC-ID)
Read ID (RDID)
11
Enable SO to output
RY/
Status during AAI
(EBSY)
Disable SO to output
Status during AAI
RY/
(DBSY)
Bus Cycle
1~3
1
2
3
4
S
OUT
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
IN
33
MHz
03H Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
X
0BH Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
X
Max.
Freq
3BH
20H
D8H
60H /
C7H
02H
ADH
05H
50H
01H
06H
04H
B1H
ABH
ABH
ABH
9FH
90H
70H
A
23
-A
16
A
15
-A
8
A
7
-A
0
-
-
-
D
IN0
D
IN0
-
-
-
-
-
-
-
-
-
-
X
X
-
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
Hi-Z
-
-
-
-
-
-
5
S
OUT
D
OUT0
X
X
-
-
-
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
8CH
13H
-
-
-
-
D
IN1
D
IN1
-
-
-
-
-
-
-
-
-
-
X
X
-
S
IN
X
X
6
S
OUT
D
OUT1
D
OUT0
-
-
-
Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
13H
8CH
-
S
IN
N
S
OUT
X
X
-
-
-
cont.
cont.
-
-
-
D
OUT0~1
cont.
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
Hi-Z A
23
-A
16
Hi-Z A
15
-A
8
Hi-Z A
7
-A
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
-
D
IN
-
-
-
X
X
X
X
00H
-
D
OUT
-
Hi-Z
-
-
-
13H
33H
73H
8CH
Hi-Z
-
-
-
-
-
-
-
-
-
-
X
00H
-
-
-
-
-
-
-
-
-
-
20H
Hi-Z
-
-
-
-.
-
-
-.
-
-.
-.
X
00H
01H
-
-
-
-
-
-
-
-
-
-
14H
Hi-Z
Hi-Z
-
Up to
256 Hi-Z
bytes
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
80H
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
Elite Semiconductor Memory Technology Inc.
Publication Date:
Jul. 2009
Revision: 1.7
8/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
