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F25L008A-50PAG 参数 Datasheet PDF下载

F25L008A-50PAG图片预览
型号: F25L008A-50PAG
PDF下载: 下载PDF文件 查看货源
内容描述: 8Mbit的( 1Mx8 ) 3V只有串行闪存 [8Mbit (1Mx8) 3V Only Serial Flash Memory]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 31 页 / 359 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F25L008A  
47  
4KB  
:
02F000H – 02FFFFH  
2
1
0
0
0
0
0
0
0
1
0
0
0
1
0
:
:
32  
31  
:
4KB  
4KB  
:
020000H – 020FFFH  
01F000H – 01FFFFH  
:
16  
15  
:
4KB  
4KB  
:
010000H – 010FFFH  
00F000H – 00FFFFH  
:
0
4KB  
000000H – 000FFFH  
Table2 : F25L008A Block Protection Table  
TOP  
Protection Level  
Status Register Bit  
Protected Memory Area  
Block Range Address Range  
BP2  
0
BP1  
0
BP0  
0
0
None  
None  
Upper 1/16  
Upper 1/8  
Upper 1/4  
Upper 1/2  
All Blocks  
All Blocks  
All Blocks  
0
0
1
Block 15  
F0000H – FFFFFH  
E0000H – FFFFFH  
C0000H – FFFFFH  
80000H – FFFFFH  
00000H – FFFFFH  
00000H – FFFFFH  
00000H – FFFFFH  
0
1
0
Block 14~15  
Block 12~15  
Block 8~15  
Block 0~15  
Block 0~15  
Block 0~15  
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
BOTTOM  
Protection Level  
Status Register Bit  
Protected Memory Area  
BP2  
BP1  
0
BP0  
Block Range  
None  
Address Range  
None  
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
Bottom 1/16  
Bottom 1/8  
Bottom 1/4  
Bottom 1/2  
All Blocks  
All Blocks  
All Blocks  
0
Block 0  
00000H – 0FFFFH  
00000H – 1FFFFH  
00000H – 3FFFFH  
00000H – 7FFFFH  
00000H – FFFFFH  
00000H – FFFFFH  
00000H – FFFFFH  
1
Block 0~1  
Block 0~3  
Block 0~7  
Block 0~15  
Block 0~15  
Block 0~15  
1
0
0
1
1
Block Protection (BP2, BP1, BP0)  
Block Protection Lock-Down (BPL)  
The Block-Protection (BP2, BP1, BP0) bits define the size of the  
memory area, as defined in Table2 to be software protected  
against any memory Write (Program or Erase) operations. The  
Write-Status-Register (WRSR) instruction is used to program the  
WP pin driven low (VIL), enables the Block-Protection  
-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any  
further alteration of the BPL, BP2, BP1, and BP0 bits. When the  
WP pin is driven high (VIH), the BPL bit has no effect and its  
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.  
BP2, P1, BP0 bits as long as WP is high or the  
Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be  
executed if Block-Protection bits are all 0. After power-up, BP2,  
BP1 and BP0 are set to1.  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May. 2007  
Revision: 1.4 5/31  
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