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F25L008A-50PAG 参数 Datasheet PDF下载

F25L008A-50PAG图片预览
型号: F25L008A-50PAG
PDF下载: 下载PDF文件 查看货源
内容描述: 8Mbit的( 1Mx8 ) 3V只有串行闪存 [8Mbit (1Mx8) 3V Only Serial Flash Memory]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 31 页 / 359 K
品牌: ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
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ESMT  
F25L008A  
Status Register  
The software status register provides status on whether the flash  
memory array is available for any Read or Write operation,  
whether the device is Write enabled, and the state of the memory  
Write protection. During an internal Erase or Program operation,  
the status register may be read only to determine the completion  
of an operation in progress.  
Table 4 describes the function of each bit in the software status  
register.  
TABLE 4: SOFTWARE STATUS REGISTER  
Default at  
Read/Write  
Power-up  
Bit  
Name  
BUSY  
WEL  
Function  
1 = Internal Write operation is in progress  
0 = No internal Write operation is in progress  
0
0
0
R
R
1 = Device is memory Write enabled  
0 = Device is not memory Write enabled  
1
2
3
4
5
BP0  
BP1  
BP2  
Indicate current level of block write protection (See Table 5)  
Indicate current level of block write protection (See Table 5)  
Indicate current level of block write protection (See Table 5)  
1
1
1
0
R/W  
R/W  
R/W  
N/A  
RESERVED Reserved for future use  
Auto Address Increment Programming status  
1 = AAI programming mode  
6
7
AAI  
0
0
R
0 = Byte-Program mode  
1 = BP2,BP1,BP0 are read-only bits  
0 = BP2,BP1,BP0 are read/writable  
BPL  
R/W  
Note1 : Only BP0,BP1,BP2 and BPL are writable  
Note2 : All register bits are volatility  
Note3 : All area are protected at power-on (BP2=BP1=BP0=1)  
Busy  
The Busy bit determines whether there is an internal Erase or  
Program operation in progress. A “1” for the Busy bit indicates  
the device is busy with an operation in progress. A “0” indicates  
the device is ready for the next valid operation.  
Write Enable Latch (WEL)  
The Write-Enable-Latch bit indicates the status of the internal  
memory Write Enable Latch. If the Write-Enable-Latch bit is set to  
“1”, it indicates the device is Write enabled. If the bit is set to “0”  
(reset), it indicates the device is not Write enabled and does not  
accept any memory Write (Program/ Erase) commands. The  
Write-Enable-Latch bit is automatically reset under the following  
conditions:  
Power-up  
Write-Disable (WRDI) instruction completion  
Byte-Program instruction completion  
Auto Address Increment (AAI) programming reached its  
highest memory address  
Sector-Erase instruction completion  
Block-Erase instruction completion  
Chip-Erase instruction completion  
Write-Status-Register instructions  
Elite Semiconductor Memory Technology Inc.  
Publication Date: May. 2007  
Revision: 1.4 8/31  
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