ESMT
F25L004A
64K-Byte Block-Erase
The 64K Byte Block-Erase instruction clears all bits in the
selected block to FFH. A Block-Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
[A23-A0]. Address bits [AMS-A16] (AMS = Most Significant address)
are used to determine the block address (BAX), remaining
address bits can be VIL or VIH. CE must be driven high before
the instruction is executed. The user may poll the Busy bit in the
software status register or wait TBE for the completion of the
internal self-timed Block-Erase cycle. See Figure 9 for the
Block-Erase sequence.
executed. CE must remain active low for the duration of the any
command sequence. The Block-Erase instruction is initiated by
executing an 8-bit command, D8H, followed by address bits
FIGURE 9 : 64-KBYTE BLOCK-ERASE SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2007
Revision: 1.2
15/32
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
